System Performance (Cambridge (CIE) A Level Computer Science) : Revision Note

Robert Hampton

Written by: Robert Hampton

Reviewed by: James Woodhouse

Updated on

Cores

What is a core?

  • A core acts like a mini CPU, it can fetch, decode, and execute instructions on its own

  • Each core has its own:

    • Control Unit (CU)

    • Arithmetic Logic Unit (ALU)

    • Registers

  • A CPU with more than one core is a multicore CPU

  • Allows for parallel processing, multiple instructions are processed at the same time

  • Example:

    • A dual-core processor has 2 cores

    • A quad-core processor has 4 cores

  • More cores = better performance, especially for powerful programs

    Example:

    • A quad-core CPU running at 3GHz

    • 4 cores × 3 billion = 12 billion instructions per second

  • A dual-core processor isn't always twice as fast as a single-core

    • Some time is used for organising tasks between cores

  • Not all tasks can be split across cores

    • Some tasks are sequential and must be done step-by-step

cpu-cores-

Clock speed

What is clock speed?

  • The clock controls the timing of operations inside the CPU

  • It constantly switches between 0 and 1, each switch is called a state change

  • A state change can represent one step in the fetch-decode-execute cycle

    • Some instructions may take more than one cycle

  • Clock speed measures how many state changes happen per second

  • 1 cycle per second = 1 Hz

  • A typical clock speed is around 2.3 GHz

    • That’s 2.3 billion cycles per second

  • A higher clock speed means the CPU can execute more instructions per second

  • This helps the computer run tasks more quickly and efficiently

Image of the CPU


Cache memory

What is cache memory?

  • Cache is part of primary storage

  • Stores frequently used data and instructions

  • Located closer to the CPU than RAM, so it’s faster to access

  • Some cache is built directly into each processor core

  • Speeds up the performance of the CPU

  • More cache = more data stored nearby = less time waiting for data from RAM

  • Example:

    • A website you visit often can be stored in the cache

    • Next time you visit, it loads faster

    • If the website updates, the cached version is updated too

Levels of cache

Level

Location

Speed

Size

Level 1 (L1)

Inside each CPU core

Fastest

Smallest

Level 2 (L2)

Inside or near each core

Fast

Medium

Level 3 (L3)

Shared by all cores

Slower than L1/L2

Largest

Diagram illustrating CPU cache levels: L1 (small, fast, per core), L2 (shared, slower, larger), L3 (slower, larger, on motherboard).
Diagram of the levels within the cache

Bus width

What is bus width?

  • Bus width is the number of bits a bus can carry at once

  • A wider bus can transfer more bits in a single operation

  • Example:

    • A 32-bit bus transfers 32 bits at a time

    • A 64-bit bus transfers 64 bits at a time

  • Increases performance, more data can be moved in the same amount of time

  • A wider data bus means:

    • Faster processing

    • More efficient memory access

  • Important for high-performance tasks like gaming, video editing, or large data processing

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Robert Hampton

Author: Robert Hampton

Expertise: Computer Science Content Creator

Rob has over 16 years' experience teaching Computer Science and ICT at KS3 & GCSE levels. Rob has demonstrated strong leadership as Head of Department since 2012 and previously supported teacher development as a Specialist Leader of Education, empowering departments to excel in Computer Science. Beyond his tech expertise, Robert embraces the virtual world as an avid gamer, conquering digital battlefields when he's not coding.

James Woodhouse

Reviewer: James Woodhouse

Expertise: Computer Science Lead

James graduated from the University of Sunderland with a degree in ICT and Computing education. He has over 14 years of experience both teaching and leading in Computer Science, specialising in teaching GCSE and A-level. James has held various leadership roles, including Head of Computer Science and coordinator positions for Key Stage 3 and Key Stage 4. James has a keen interest in networking security and technologies aimed at preventing security breaches.